(a) Field of the Invention
The present invention relates to a digital phase locked loop (DPLL) circuit, and more particularly, to a DPLL circuit for recovering a 27 MHz system clock on the basis of a program clock reference (PCR) received in a demutiplexer of an MPEG2 system or a HDTV.
(b) Description of the Related Art
In a system using the MPEG2 standard or in HDTVs, data is packetized then transmitted through a transport stream (TS). In order to synchronize the data in a receiving part of the MPEG2 system or HDTV, an encoder codes the data on the basis of a 27 MHz system clock.
However, when transporting data through the TS, as a result of either a delay in the signal or influence received from the transport path, a time base of the receiving part becomes different from the transmission timing. Accordingly, buffer overflow or underflow occurs during decoding such that data can not be precisely recovered.
It is therefore necessary to have a predetermined delay between the encoder and a decoder, during which the data timing is found and recovered. A DPLL is used by one of the methods performing this operation. In this method, in order to synchronize a transmitting clock with a receiving clock using a DPLL, a counter value (i.e., a PCR value), driven by 27 MHz, is included in the TS in the transmitting end, then transmitted. Next, the PCR value is received in a DPLL of the receiving part, and using this as a basis, a system clock of 27 MHz is recovered.
Referring to FIG. 1, shown is a conventional DPLL circuit. As shown in the drawing, the conventional DPLL circuit comprises a PCR register 10 for receiving and storing a program standard clock; an LPCR (local program clock reference) counter counting by a system clock; an LPCR register 20 which fetches the LPCR counter value every PCR input cycle; a phase error detector 11 for obtaining a phase error using a PCR value and an LPCR value stored in the PCR register 10 and the LPCR register 20, respectively; a multiplier 12 for multiplying the output of the phase error detector 11 by a predetermined gain 13; an interpolator 14 receiving output of the multiplier 12 and interpolating a value between a previous input value and a present input value; a digital-analog converter (DAC) 15 receiving output of the interpolator 14 to generate a PWM output signal; a low-pass filter 16 receiving the pulse width modulation (PWM) output signal from the DAC 15, and removing high-frequency band signal components from the same to generate a mean signal voltage; a voltage controlled oscillator (VCO) 17 for generating frequencies in a predetermined range from 27 MHz according to the signal voltage of the low-pass filter 16; a divider 18 dividing the 27 MHz system clock frequencies for the supply as clock frequencies of the interpolator 14 and the DAC 15; an LPCR counter 19 using a clock output of the VCO 17; and a system time clock (STC) circuit 21 for adding a difference between the PCR base value and the LPCR base value to a base value of the LPCR, and outputting the resulting value.
However, in the conventional DPLL circuit as shown in FIG. 1, the process of (a) calculating a value of the difference between the presently-input PCR (PCRn) and the PCR input before the cycle (PCRn-1) every PCR cycle (.DELTA.PCR=PCRn-PCRn-1); (b) reading the LPCR counter value, driven by the recovered 27 MHz, every time the PCR is input; and (c) calculating a value of the difference between the presently-input LPCR (LPCRn) and the directly prior LPCR (LPCRn-1) must be performed using software.
Further, the calculation to obtain the phase error ##EQU1## must also be performed using software. In addition to these calculations, the multiplication of the gain and the interpolating calculations are also performed using software.
As a result, a micro-controller must be employed to perform the computation of all the above calculations (.DELTA.PCR value, .DELTA.LPCR value, PHASEerr value, gain multiplication, and interpolation), thereby increasing overall manufacturing costs of the conventional DPLL circuit. In addition, application to other products is not easy, and operational speed is reduced.
Also, as a predetermined loop gain is multiplied to the PHASEerr before interpolation, in order to lock the DPLL circuit for stabilization of the same, a quantization error occurs before interpolation.
And finally, in the conventional DPLL circuit, since a predetermined gain is multiplied without relation to PCR intervals, the lock-up time changes according to PCR input.